Semiconductor devices are typically classified as either volatile semiconductor devices, which require power to maintain storage of data, or non-volatile semiconductor devices, which can retain data even upon removal of a power source. An example non-volatile semiconductor device is a flash memory device, which generally includes a matrix of memory cells arranged in rows and columns. Each memory cell in the matrix includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. Each memory cell is located at an intersection between a word line and a bit line, wherein the gate is connected to the word line, the drain is connected to the bit line, and the source is connected to a source line, which in turn is connected to common ground. The gate of a conventional flash memory cell generally comprises a dual-gate structure, including a control gate and a floating gate, wherein the floating gate is suspended between two oxide layers to trap electrons that program the cell.
Flash memory devices may in turn be classified as NOR or NAND flash memory devices. Of these, NOR flash memory typically offers faster program and read speeds whereby each cell connects to ground at one end and connects to the bit line at the other end. Using conventional manufacturing methods, NOR and NAND flash take a 2D form by which the memory cells are created in a two dimensional array on a silicon substrate. However, the 2D architecture has demonstrated limitations, such as the scaling limitations encountered due to the process and device restrictions. Therefore, a 3D architecture, which stacks cells on top of each other, has been developed with respect to 3D NAND flash offering faster program and erase. Accordingly, there is a need in the art to increase the scalability of performance of read operations and maximize the data capacity properties of 3D NOR devices.